Cheshire: A Lightweight, Linux-Capable RISC-V Host Platform for Domain-Specific Accelerator Plug-In

Power and cost constraints in the internet-of-things (IoT) extreme-edge TinyML domains, coupled with increasing performance requirements, motivate a trend toward heterogeneous architectures. These designs use energy-efficient application-class host processors to coordinate compute-specialized multicore accelerators, amortizing architectural costs of operating system support external communication. This brief presents Cheshire, lightweight modular 64-bit Linux-capable platform designed for seamless plug-in domain-specific accelerators. It features unique low-pin-count DRAM interface, last-level cache configurable as scratchpad memory, DMA engine enabling efficient data movement or from accelerators DRAM. also provides numerous optional IO peripherals including UART, SPI, I2C, VGA, GPIOs. Cheshire’s synthesizable RTL description, comprising all its fully digital is available free open-source. We implemented fabricated Cheshire silicon demonstrator called Neo TSMC’s 65nm CMOS technology. At 1.2 V, achieves clock frequencies up 325 MHz while not exceeding 300 mW total power on data-intensive computational workloads. Its RPC interface consumes only 250 pJ/B incurs 3.5 kGE area PHY attaining peak transfer rate 750 MB/s at 200 MHz.